Computing and electronic devices continue to get smaller, even while performance remains the same or increases. Smaller computing and electronic devices are made possible by smaller electronic components due to smaller geometries on the components. Manufacturing processes can currently generate components that have a large number of I/O (input/output) signal lines in an I/O interface, and with a smaller pitch between the signal lines than is practically possible to contact for direct AC and DC performance testing. DC (direct current) performance settings refers to biasing and/or voltage levels associated with the signaling, while AC (alternating current) performance refers to the timing of the edges of the signals over the interface, where testing for AC performance can be referred to as margining.
The decreasing size of the electronic components and the pitch between signal lines increases the difficulty of testing the devices. For many devices, the number of signal lines and the small pitch makes it impractical to directly test the I/O interface. A lack of direct testing has increased the risk that device manufacturers will not be able to achieve ultralow defects per million (DPM) targets with traditional testing. One specific area of technology in which such risks are currently being presented is with wide interface memory devices. Available testing methods are not practical in mass production (e.g., HVM (high volume manufacturing)) where the time required to test devices serially would be prohibitive.
The manufacturers of the electronic component chips (e.g., such as DRAM (dynamic random access memory) suppliers) test the I/O interface or the I/O signal array. Traditional methods for testing I/O AC timing are structural testing that attempt to exercise a particular electronic component block. Structural testing requires different tests for each different component and/or element of a circuit block. Structural testing does not capture noise, making the testing results optimistic if not outright incorrect. Traditional testing relies on margining on a single data bit within a burst pattern. Traditional testing methods screen for outliers in AC timings (e.g., setup and hold timing margins at the receiver), but are very slow and costly.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.